专利摘要显示，本申请涉及集成电路技术领域，尤其涉及一种冗余校准方法、装置以及终端设备，该方法应用于下极板采样的 SAR ADC 电路，该下极板采样的 SAR ADC 电路包括单端 SAR ADC 电路和差分 SAR ADC 电路，该方法包括：基于多个采样电容的下极板对二进制电容阵列进行采样操作；在完成采样操作后，按照预设的高位到低位序次对二进制电容阵列进行数模转换，得到冗余电容的冗余位比较结果，和各采样电容各自的非冗余位比较结果；将冗余位比较结果叠加在多个非冗余位比较结果上，以对比较器的输出二进制码进行校准。本申请冗余校准方法应用于 SAR ADC 电路上有效地提高了 SAR ADC 电路的输出结构进行校准的的准确性。
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